----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:44:51 06/05/2012 
-- Design Name: 
-- Module Name:    TARGET4_TDC - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--		Testing Time-to-Digital Convertor method for triggers.
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TARGET4_TDC is
	generic (
		constant BIT_WIDTH : integer := 32		
			);
	port (
		CLK			: IN STD_LOGIC;
		RST			: IN STD_LOGIC;
		
		TRG			: IN STD_LOGIC;
		
		DONE			: OUT	
		CNT_TDC		: OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
		
		
	);

end TARGET4_TDC;

architecture Behavioral of TARGET4_TDC is
	-----------------FIFO 32*128---------------------------------
	COMPONENT FIFO
	  PORT (
		 clk : IN STD_LOGIC;
		 rst : IN STD_LOGIC;
		 din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		 wr_en : IN STD_LOGIC;
		 rd_en : IN STD_LOGIC;
		 dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		 full : OUT STD_LOGIC;
		 empty : OUT STD_LOGIC
	  );
	END COMPONENT;
	-------------------------------------------------------------
	
	component D_FLIP_FLOP
		PORT(
			CLK : IN STD_LOGIC;
			RST : IN STD_LOGIC;
			D	 : IN STD_LOGIC;
			
			Q	 : OUT STD_LOGIC
		);
	end component;
	
	component JK_FLIP_FLOP
		PORT(
			CLK : IN STD_LOGIC;
			RST : IN STD_LOGIC;
			J	 : IN STD_LOGIC;
			K	 : IN STD_LOGIC;
			Q	 : OUT STD_LOGIC
		);
	end component;
	-------------------------------------------------------------
	SIGNAL			cnt		: UNSIGNED(WIDTH-1 DOWNTO 0);
	SIGNAL			fifo_in	: STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
	SIGNAL			fifo_out	: STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
begin
	-------------------------------------
	FIFO_TDC : FIFO
	  PORT MAP (
		 clk => clk,
		 rst => rst,
		 din => fifo_in,
		 wr_en => WR_EN,
		 rd_en => rd_en,
		 dout => fifo_out,
		 full => full,
		 empty => empty
	  );
	-------------------------------------
	DFF1	: D_FLIP_FLOP
		PORT MAP (
			CLK => CLK,
			RST => RST,
			D	 => TRG,	--TRIGGER OUTPUT FROM ASIC.
			Q	 => Q1
		);
	DFF2	: D_FLIP_FLOP
		PORT MAP (
			CLK => CLK,
			RST => RST,
			D	 => Q1,	--OUTPUT FROM DFF1
			Q	 => Q2
		);
	JKFF	: JK_FLIP_FLOP
		PORT MAP (
			CLK => CLK,
			RST => RST,
			J	 => Q1,
			K	 => Q2,
			Q	 =>
		);
	-------------------------------------
	COUNTER	: PROCESS(CLK, TRG)
	BEGIN
		if RST = '1' THEN
			cnt <= (OTHERS => '0');
		elsif rising_edge(CLK) then	
			cnt <= cnt + 1;
			
			if TRG = '1' then
				
			end if;
		end if;
	END PROCESS COUNTER;
	--------------------------------------
	WR_EN_CONTROL	: PROCESS(CLK)
	BEGIN
		if falling_edge(CLK) then	
			
			
		end if;
	END PROCESS WR_EN_CONTROL;
	-------------------------------------
	
	FIFO_INPUT	: PROCESS(TRG)
	BEGIN
		if rising_edge(TRG) then
			fifo_in	<= STD_LOGIC_VECTOR(cnt);
		end if;
	END PROCESS FIFO_INPUT;
	-------------------------------------
	
end Behavioral;

